Abstract
Based on a modified step-by-step decoding procedure, a high-speed pipelined Reed-Solomon decoder is presented. The decoder requires only the delay time of three 2-input XOR gates for decoding each coded symbol. The decoder can be operated in a bit rate of Gbits/sec order and thus suitable for the very high speed data transmission systems.
| Original language | English |
|---|---|
| Pages (from-to) | 847-849 |
| Number of pages | 3 |
| Journal | IEICE Transactions on Communications |
| Volume | E86-B |
| Issue number | 2 |
| Publication status | Published - 2003 Feb |
All Science Journal Classification (ASJC) codes
- Software
- Computer Networks and Communications
- Electrical and Electronic Engineering
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Chen, T. C., Wei, C. H., & Wei, S. W. (2003). A pipeline structure for high-speed step-by-step RS decoding. IEICE Transactions on Communications, E86-B(2), 847-849.