A peak current and power pad count reduction tool for system-level IC designers

Tsung Yi Wu, Tzi Wei Kao, Shi Yi Huang, Tai Lun Li, How Rern Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. The goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.

Original languageEnglish
Title of host publication2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
Pages128-129
Number of pages2
DOIs
Publication statusPublished - 2009 Oct 27
Event2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 - Kyoto, Japan
Duration: 2009 May 252009 May 28

Other

Other2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
CountryJapan
CityKyoto
Period09-05-2509-05-28

Fingerprint

Clocks
Networks (circuits)
Transistors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

Wu, T. Y., Kao, T. W., Huang, S. Y., Li, T. L., & Lin, H. R. (2009). A peak current and power pad count reduction tool for system-level IC designers. In 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 (pp. 128-129). [5156905] https://doi.org/10.1109/ISCE.2009.5156905
Wu, Tsung Yi ; Kao, Tzi Wei ; Huang, Shi Yi ; Li, Tai Lun ; Lin, How Rern. / A peak current and power pad count reduction tool for system-level IC designers. 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. 2009. pp. 128-129
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title = "A peak current and power pad count reduction tool for system-level IC designers",
abstract = "In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. The goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3{\%} and reduce the power pad count up to 40.0{\%}.",
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Wu, TY, Kao, TW, Huang, SY, Li, TL & Lin, HR 2009, A peak current and power pad count reduction tool for system-level IC designers. in 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009., 5156905, pp. 128-129, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009, Kyoto, Japan, 09-05-25. https://doi.org/10.1109/ISCE.2009.5156905

A peak current and power pad count reduction tool for system-level IC designers. / Wu, Tsung Yi; Kao, Tzi Wei; Huang, Shi Yi; Li, Tai Lun; Lin, How Rern.

2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. 2009. p. 128-129 5156905.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Wu TY, Kao TW, Huang SY, Li TL, Lin HR. A peak current and power pad count reduction tool for system-level IC designers. In 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. 2009. p. 128-129. 5156905 https://doi.org/10.1109/ISCE.2009.5156905