A novel high speed Chinese abacus multiplier

Yi Chieh Lin, Chien Hung Lin, Zi Yi Zhao, Yu Zhi Xie, Yen Ju Chen, Shu-chung Yi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18μm technology.

Original languageEnglish
Title of host publicationIMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007
Pages510-513
Number of pages4
Publication statusPublished - 2007 Dec 1
EventInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007 - Kowloon, Hong Kong
Duration: 2007 Mar 212007 Mar 23

Other

OtherInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007
CountryHong Kong
CityKowloon
Period07-03-2107-03-23

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)

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