A novel high speed Chinese abacus multiplier

Yi Chieh Lin, Chien Hung Lin, Zi Yi Zhao, Yu Zhi Xie, Yen Ju Chen, Shu-chung Yi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18μm technology.

Original languageEnglish
Title of host publicationIMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007
Pages510-513
Number of pages4
Publication statusPublished - 2007 Dec 1
EventInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007 - Kowloon, Hong Kong
Duration: 2007 Mar 212007 Mar 23

Other

OtherInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007
CountryHong Kong
CityKowloon
Period07-03-2107-03-23

Fingerprint

Time delay
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)

Cite this

Lin, Y. C., Lin, C. H., Zhao, Z. Y., Xie, Y. Z., Chen, Y. J., & Yi, S. (2007). A novel high speed Chinese abacus multiplier. In IMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007 (pp. 510-513)
Lin, Yi Chieh ; Lin, Chien Hung ; Zhao, Zi Yi ; Xie, Yu Zhi ; Chen, Yen Ju ; Yi, Shu-chung. / A novel high speed Chinese abacus multiplier. IMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007. 2007. pp. 510-513
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abstract = "In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63{\%} less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51{\%} less than that of Braun array multiplier for 0.18μm technology.",
author = "Lin, {Yi Chieh} and Lin, {Chien Hung} and Zhao, {Zi Yi} and Xie, {Yu Zhi} and Chen, {Yen Ju} and Shu-chung Yi",
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Lin, YC, Lin, CH, Zhao, ZY, Xie, YZ, Chen, YJ & Yi, S 2007, A novel high speed Chinese abacus multiplier. in IMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007. pp. 510-513, International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, Kowloon, Hong Kong, 07-03-21.

A novel high speed Chinese abacus multiplier. / Lin, Yi Chieh; Lin, Chien Hung; Zhao, Zi Yi; Xie, Yu Zhi; Chen, Yen Ju; Yi, Shu-chung.

IMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007. 2007. p. 510-513.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Lin, Yi Chieh

AU - Lin, Chien Hung

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AU - Yi, Shu-chung

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N2 - In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18μm technology.

AB - In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18μm technology.

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Lin YC, Lin CH, Zhao ZY, Xie YZ, Chen YJ, Yi S. A novel high speed Chinese abacus multiplier. In IMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007. 2007. p. 510-513