A new placement algorithm for custom chip design

A placement algorithm which consists of three subalgorithms--an O(kn²) circle model relative placement algorithm, an O(n² log n triangulation algorithm, and an O(n² log n²) optimal slicing algorithm for custom chip design--is presented. This relative placement algorithm addresses size effect and net connectivity effect simultaneously, while attaining a low polynomial time complexity O(kn²) without loss of global perspective, where k is a constant and depends on the accuracy that the placement required. The triangulation algorithm has O(n² log n) time complexity. The triangulated planar graph can be used to do the floorplan by either the nonslicing RDG (rectangular dual graph) or slicing embedding methods. The optimum slicing algorithm has O(n² log n²) time complexity. As expected, the wire length of the placement algorithm is shorter than that of a point model. However, since the optimal values of l₀ and DEF (deformation ratio) are unknown, different values for l₀ and DEF should be used in different circuits to obtain better placement results.