### Abstract

A placement algorithm which consists of three subalgorithms--an O(kn^{2}) circle model relative placement algorithm, an O(n^{2} log n triangulation algorithm, and an O(n^{2} log n^{2}) optimal slicing algorithm for custom chip design--is presented. This relative placement algorithm addresses size effect and net connectivity effect simultaneously, while attaining a low polynomial time complexity O(kn^{2}) without loss of global perspective, where k is a constant and depends on the accuracy that the placement required. The triangulation algorithm has O(n^{2} log n) time complexity. The triangulated planar graph can be used to do the floorplan by either the nonslicing RDG (rectangular dual graph) or slicing embedding methods. The optimum slicing algorithm has O(n^{2} log n^{2}) time complexity. As expected, the wire length of the placement algorithm is shorter than that of a point model. However, since the optimal values of l_{0} and DEF (deformation ratio) are unknown, different values for l_{0} and DEF should be used in different circuits to obtain better placement results.

Original language | English |
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Pages (from-to) | 1672-1675 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 3 |

Publication status | Published - 1990 Dec 1 |

Event | 1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA Duration: 1990 May 1 → 1990 May 3 |

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### All Science Journal Classification (ASJC) codes

- Electrical and Electronic Engineering

### Cite this

*Proceedings - IEEE International Symposium on Circuits and Systems*,

*3*, 1672-1675.

}

*Proceedings - IEEE International Symposium on Circuits and Systems*, vol. 3, pp. 1672-1675.

**A new placement algorithm for custom chip design.** / Lin, Zhi-Ming; Lin, Hung C.

Research output: Contribution to journal › Conference article

TY - JOUR

T1 - A new placement algorithm for custom chip design

AU - Lin, Zhi-Ming

AU - Lin, Hung C.

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A placement algorithm which consists of three subalgorithms--an O(kn2) circle model relative placement algorithm, an O(n2 log n triangulation algorithm, and an O(n2 log n2) optimal slicing algorithm for custom chip design--is presented. This relative placement algorithm addresses size effect and net connectivity effect simultaneously, while attaining a low polynomial time complexity O(kn2) without loss of global perspective, where k is a constant and depends on the accuracy that the placement required. The triangulation algorithm has O(n2 log n) time complexity. The triangulated planar graph can be used to do the floorplan by either the nonslicing RDG (rectangular dual graph) or slicing embedding methods. The optimum slicing algorithm has O(n2 log n2) time complexity. As expected, the wire length of the placement algorithm is shorter than that of a point model. However, since the optimal values of l0 and DEF (deformation ratio) are unknown, different values for l0 and DEF should be used in different circuits to obtain better placement results.

AB - A placement algorithm which consists of three subalgorithms--an O(kn2) circle model relative placement algorithm, an O(n2 log n triangulation algorithm, and an O(n2 log n2) optimal slicing algorithm for custom chip design--is presented. This relative placement algorithm addresses size effect and net connectivity effect simultaneously, while attaining a low polynomial time complexity O(kn2) without loss of global perspective, where k is a constant and depends on the accuracy that the placement required. The triangulation algorithm has O(n2 log n) time complexity. The triangulated planar graph can be used to do the floorplan by either the nonslicing RDG (rectangular dual graph) or slicing embedding methods. The optimum slicing algorithm has O(n2 log n2) time complexity. As expected, the wire length of the placement algorithm is shorter than that of a point model. However, since the optimal values of l0 and DEF (deformation ratio) are unknown, different values for l0 and DEF should be used in different circuits to obtain better placement results.

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UR - http://www.scopus.com/inward/citedby.url?scp=0025692944&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0025692944

VL - 3

SP - 1672

EP - 1675

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -