A new pinched-off cold-FET method to determine parasitic capacitances of FET equivalent circuits

Yeong Lin Lai; Kuo Hua Hsu

doi:10.1109/22.939921

A new pinched-off cold-FET method to determine parasitic capacitances of FET equivalent circuits

Yeong Lin Lai, Kuo Hua Hsu

Department of Mechatronic Engineering

Research output: Contribution to journal › Conference article › peer-review

31 Citations (Scopus)

Abstract

A new pinched-off cold FET method to extract the parasitic capacitances of FETs is proposed in this paper. The method is based on a physically meaningful depletion-layer model and the theoretical analysis of the two-port network for the pinched-off cold FETs. The parasitic gate capacitance (C _pg) and the parasitic drain capacitance (C _pd) of FETs are extracted using the linear regression technique associated with the frequency responses of Y-parameters. The extraction method can be applied to the small-signal equivalent-circuit modeling of the FETs including MESFETs, heterojunction FETs, and high-electron-mobility transistors. According to the new analytical method, the simulated S-parameters exhibit great agreement with the measured S-parameters for the equivalent-circuit models of FETs.

Original language	English
Pages (from-to)	1410-1418
Number of pages	9
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	49
Issue number	8
DOIs	https://doi.org/10.1109/22.939921
Publication status	Published - 2001 Aug 1
Event	2000 IEEE Radio and Wireless Conference (RAWCON) - Denver, CO, United States Duration: 2001 Sep 10 → 2001 Oct 13

All Science Journal Classification (ASJC) codes

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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abstract = "A new pinched-off cold FET method to extract the parasitic capacitances of FETs is proposed in this paper. The method is based on a physically meaningful depletion-layer model and the theoretical analysis of the two-port network for the pinched-off cold FETs. The parasitic gate capacitance (C pg) and the parasitic drain capacitance (C pd) of FETs are extracted using the linear regression technique associated with the frequency responses of Y-parameters. The extraction method can be applied to the small-signal equivalent-circuit modeling of the FETs including MESFETs, heterojunction FETs, and high-electron-mobility transistors. According to the new analytical method, the simulated S-parameters exhibit great agreement with the measured S-parameters for the equivalent-circuit models of FETs.",

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