A multiplier based on the algorithm of chinese abacus

Chien Hung Lin, Shu-chung Yi, Jin-Jia Chen

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.

Original languageEnglish
Pages (from-to)11-22
Number of pages12
JournalWSEAS Transactions on Electronics
Volume6
Issue number1
Publication statusPublished - 2009 Jan 1

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Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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A multiplier based on the algorithm of chinese abacus. / Lin, Chien Hung; Yi, Shu-chung; Chen, Jin-Jia.

In: WSEAS Transactions on Electronics, Vol. 6, No. 1, 01.01.2009, p. 11-22.

Research output: Contribution to journalArticle

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N2 - A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.

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