A multiplier based on the algorithm of chinese abacus

Chien Hung Lin; Shu-chung Yi; Jin-Jia Chen

A multiplier based on the algorithm of chinese abacus

Chien Hung Lin, Shu-chung Yi, Jin-Jia Chen

Research output: Contribution to journal › Article › peer-review

Abstract

A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.

Original language	English
Pages (from-to)	11-22
Number of pages	12
Journal	WSEAS Transactions on Electronics
Volume	6
Issue number	1
Publication status	Published - 2009 Jan 1

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

Fingerprint Dive into the research topics of 'A multiplier based on the algorithm of chinese abacus'. Together they form a unique fingerprint.

Cite this

@article{4dfb18203fa34f0496dc227543bf1b35,

title = "A multiplier based on the algorithm of chinese abacus",

abstract = "A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35{\`i}m and 0.18{\`i}m technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.",

author = "Lin, {Chien Hung} and Shu-chung Yi and Jin-Jia Chen",

year = "2009",

month = jan,

day = "1",

language = "English",

volume = "6",

pages = "11--22",

journal = "WSEAS Transactions on Electronics",

issn = "1109-9445",

publisher = "World Scientific and Engineering Academy and Society",

number = "1",

}

TY - JOUR

T1 - A multiplier based on the algorithm of chinese abacus

AU - Lin, Chien Hung

AU - Yi, Shu-chung

AU - Chen, Jin-Jia

PY - 2009/1/1

Y1 - 2009/1/1

N2 - A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.

AB - A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.

UR - http://www.scopus.com/inward/record.url?scp=77950281484&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950281484&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:77950281484

VL - 6

SP - 11

EP - 22

JO - WSEAS Transactions on Electronics

JF - WSEAS Transactions on Electronics

SN - 1109-9445

IS - 1

ER -