Abstract
A 4×4 and 8×8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4×4 and 8×8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35ìm and 0.18ìm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.
| Original language | English |
|---|---|
| Pages (from-to) | 11-22 |
| Number of pages | 12 |
| Journal | WSEAS Transactions on Electronics |
| Volume | 6 |
| Issue number | 1 |
| Publication status | Published - 2009 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Lin, C. H., Yi, S., & Chen, J-J. (2009). A multiplier based on the algorithm of chinese abacus. WSEAS Transactions on Electronics, 6(1), 11-22.