A low voltage high unity-gain bandwidth CMOS op-amp

Chih Min Yu, Zhi Ming Lin, Jun Da Chen

Research output: Contribution to conference › Paper

2 Citations (Scopus)

Abstract

This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

Original languageEnglish
Pages45-48
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 6 → 2004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-06 → 04-12-09

Fingerprint

CMOS integrated circuits
Operational amplifiers
Electric network analysis
Rails
Bandwidth
Computer simulation
Electric potential
Compensation and Redress

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Yu, C. M., Lin, Z. M., & Chen, J. D. (2004). A low voltage high unity-gain bandwidth CMOS op-amp. 45-48. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Yu, Chih Min ; Lin, Zhi Ming ; Chen, Jun Da. / A low voltage high unity-gain bandwidth CMOS op-amp. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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Yu, CM, Lin, ZM & Chen, JD 2004, 'A low voltage high unity-gain bandwidth CMOS op-amp' Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09, pp. 45-48.

A low voltage high unity-gain bandwidth CMOS op-amp. / Yu, Chih Min; Lin, Zhi Ming; Chen, Jun Da.

2004. 45-48 Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

Research output: Contribution to conference › Paper

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N2 - This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

AB - This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

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Yu CM, Lin ZM, Chen JD. A low voltage high unity-gain bandwidth CMOS op-amp. 2004. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

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