Abstract
This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.
| Original language | English |
|---|---|
| Pages | 45-48 |
| Number of pages | 4 |
| Publication status | Published - 2004 Dec 1 |
| Event | 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 2004 Dec 6 → 2004 Dec 9 |
Other
| Other | 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology |
|---|---|
| Country | Taiwan |
| City | Tainan |
| Period | 04-12-06 → 04-12-09 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Yu, C. M., Lin, Z. M., & Chen, J. D. (2004). A low voltage high unity-gain bandwidth CMOS op-amp. 45-48. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.