A low voltage high unity-gain bandwidth CMOS op-amp

Chih Min Yu; Zhi Ming Lin; Jun Da Chen

A low voltage high unity-gain bandwidth CMOS op-amp

Chih Min Yu, Zhi Ming Lin, Jun Da Chen

Department of Computer Science and Information Engineering

Research output: Contribution to conference › Paper

4 Citations (Scopus)

Abstract

This paper presents a ±1V CMOS operation amplifier with constant-g_m rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

Original language	English
Pages	45-48
Number of pages	4
Publication status	Published - 2004 Dec 1
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 2004 Dec 6 → 2004 Dec 9

Other

Other	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country	Taiwan
City	Tainan
Period	04-12-06 → 04-12-09

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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Cite this

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title = "A low voltage high unity-gain bandwidth CMOS op-amp",

abstract = "This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.",

author = "Yu, {Chih Min} and Lin, {Zhi Ming} and Chen, {Jun Da}",

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AU - Lin, Zhi Ming

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N2 - This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

AB - This paper presents a ±1V CMOS operation amplifier with constant-gm rail-to-rail input stage and class-AB output stage. The designed op-amp has been implemented in TSMC 2P4M 0.35 μm CMOS technology and simulated by Hspice. The unity-gain bandwidth of the op-amp is 13.1 MHz with Miller compensation. The slew-rate and settling time are 24V/μS and 0.48 μs, respectively. The open loop gain is 108 dB with 58 degree phase margin.

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

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