A low voltage four-quadrant CMOS analogue multiplier

Zhi-Ming Lin, C. H. Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (±0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW.

Original languageEnglish
Title of host publicationProceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1333-1335
Number of pages3
ISBN (Electronic)0780356829
DOIs
Publication statusPublished - 1999 Jan 1
Event6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 - Pafos, Cyprus
Duration: 1999 Sep 51999 Sep 8

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

Other

Other6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
CountryCyprus
CityPafos
Period99-09-0599-09-08

Fingerprint

Energy dissipation
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lin, Z-M., & Huang, C. H. (1999). A low voltage four-quadrant CMOS analogue multiplier. In Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems (pp. 1333-1335). [814415] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1999.814415
Lin, Zhi-Ming ; Huang, C. H. / A low voltage four-quadrant CMOS analogue multiplier. Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 1333-1335 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).
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Lin, Z-M & Huang, CH 1999, A low voltage four-quadrant CMOS analogue multiplier. in Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems., 814415, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1333-1335, 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, 99-09-05. https://doi.org/10.1109/ICECS.1999.814415

A low voltage four-quadrant CMOS analogue multiplier. / Lin, Zhi-Ming; Huang, C. H.

Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 1999. p. 1333-1335 814415 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lin Z-M, Huang CH. A low voltage four-quadrant CMOS analogue multiplier. In Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 1999. p. 1333-1335. 814415. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.1999.814415