A low-power direct digital frequency synthesiser

Shu Chung Yi, Jin Jia Chen, Chien Hung Lin, Kun Tse Lee

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 m DDFS with an spurious free dynamic range of -80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz-1, which represents an enhancement of more than 38% compared to the conventional DDFS.

Original languageEnglish
Pages (from-to)593-599
Number of pages7
JournalInternational Journal of Electronics
Volume95
Issue number6
DOIs
Publication statusPublished - 2008 Jan 1

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Frequency synthesizers
Table lookup
ROM
Hardware

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Yi, Shu Chung ; Chen, Jin Jia ; Lin, Chien Hung ; Lee, Kun Tse. / A low-power direct digital frequency synthesiser. In: International Journal of Electronics. 2008 ; Vol. 95, No. 6. pp. 593-599.
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A low-power direct digital frequency synthesiser. / Yi, Shu Chung; Chen, Jin Jia; Lin, Chien Hung; Lee, Kun Tse.

In: International Journal of Electronics, Vol. 95, No. 6, 01.01.2008, p. 593-599.

Research output: Contribution to journalArticle

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