This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 m DDFS with an spurious free dynamic range of -80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz-1, which represents an enhancement of more than 38% compared to the conventional DDFS.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering