A low-power architecture for the design of a one-dimensional median filter

Ren-Der Chen, Pei Yin Chen, Chun Hsien Yeh

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced.

Original languageEnglish
Article number6951341
Pages (from-to)266-270
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume62
Issue number3
DOIs
Publication statusPublished - 2015 Mar 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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