A low-power and high-linear double-balanced switching mixer

Jun Da Chen, Zhi Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The paper presents a novel topology mixer that leads to better performance in terms of linearity and power consumption for low supply voltage. Designed in umc 0.18μm CMOS technology, the mixer achieves: 4.55dB power conversion gain; 13.3dB noise figure; 4dBm input third-order intercept point (IIP3); and only 2mW of power consumption from a IV supply voltage.

Original languageEnglish
Title of host publicationGLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery (ACM)
Pages131-134
Number of pages4
ISBN (Print)1595933476, 9781595933478
DOIs
Publication statusPublished - 2006 Jan 1
EventGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States
Duration: 2006 Apr 302006 May 2

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume2006

Other

OtherGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
CountryUnited States
CityPhiladelphia, PA
Period06-04-3006-05-02

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Chen, J. D., & Lin, Z. M. (2006). A low-power and high-linear double-balanced switching mixer. In GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI (pp. 131-134). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006). Association for Computing Machinery (ACM). https://doi.org/10.1145/1127908.1127941