Abstract
The paper presents a novel topology mixer that leads to better performance in terms of linearity and power consumption for low supply voltage. Designed in umc 0.18μm CMOS technology, the mixer achieves: 4.55dB power conversion gain; 13.3dB noise figure; 4dBm input third-order intercept point (IIP3); and only 2mW of power consumption from a IV supply voltage.
| Original language | English |
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| Title of host publication | GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI |
| Pages | 131-134 |
| Number of pages | 4 |
| Publication status | Published - 2006 Nov 16 |
| Event | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States Duration: 2006 Apr 30 → 2006 May 2 |
Publication series
| Name | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
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| Volume | 2006 |
Other
| Other | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI |
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| Country | United States |
| City | Philadelphia, PA |
| Period | 06-04-30 → 06-05-02 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
Chen, J. D., & Lin, Z. M. (2006). A low-power and high-linear double-balanced switching mixer. In GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI (pp. 131-134). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).