Abstract
The paper presents a novel topology mixer that leads to better performance in terms of linearity and power consumption for low supply voltage. Designed in umc 0.18μm CMOS technology, the mixer achieves: 4.55dB power conversion gain; 13.3dB noise figure; 4dBm input third-order intercept point (IIP3); and only 2mW of power consumption from a IV supply voltage.
| Original language | English |
|---|---|
| Title of host publication | GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI |
| Pages | 131-134 |
| Number of pages | 4 |
| Publication status | Published - 2006 Nov 16 |
| Event | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States Duration: 2006 Apr 30 → 2006 May 2 |
Publication series
| Name | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
|---|---|
| Volume | 2006 |
Other
| Other | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI |
|---|---|
| Country | United States |
| City | Philadelphia, PA |
| Period | 06-04-30 → 06-05-02 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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A low-power and high-linear double-balanced switching mixer. / Chen, Jun Da; Lin, Zhi Ming.
GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI. 2006. p. 131-134 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A low-power and high-linear double-balanced switching mixer
AU - Chen, Jun Da
AU - Lin, Zhi Ming
PY - 2006/11/16
Y1 - 2006/11/16
N2 - The paper presents a novel topology mixer that leads to better performance in terms of linearity and power consumption for low supply voltage. Designed in umc 0.18μm CMOS technology, the mixer achieves: 4.55dB power conversion gain; 13.3dB noise figure; 4dBm input third-order intercept point (IIP3); and only 2mW of power consumption from a IV supply voltage.
AB - The paper presents a novel topology mixer that leads to better performance in terms of linearity and power consumption for low supply voltage. Designed in umc 0.18μm CMOS technology, the mixer achieves: 4.55dB power conversion gain; 13.3dB noise figure; 4dBm input third-order intercept point (IIP3); and only 2mW of power consumption from a IV supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=33750926085&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33750926085&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33750926085
SN - 1595933476
SN - 9781595933478
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 131
EP - 134
BT - GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
ER -