Abstract
This paper presents a design and implementation of an output buffer for LCD Driver with rail-to-rail voltage swing using TSMC 0.35 μm 2P4M process at 5V supply. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. It performs a rail-to-rail swing range and high slew rate of 14 V / μs and 11.5 V / μs for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , One is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kQ added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits the settling times of 0.7 us for rising and 0.85 μs for falling edges with voltage swing 5V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 μs and 1.80 μs for rising and falling edges , respectively. The effective area of this buffer is only 100 × 100 μm2 with build-in offset voltage holding capacitor.
| Original language | English |
|---|---|
| Title of host publication | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
| Pages | 1025-1030 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2007 Dec 1 |
| Event | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 2007 Dec 20 → 2007 Dec 22 |
Publication series
| Name | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|
Other
| Other | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|---|
| Country | Taiwan |
| City | Tainan |
| Period | 07-12-20 → 07-12-22 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
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A low offset high voltage swing rail-to-rail buffer amplifier with for LCD driver. / Hong, Guo Teng; Shen, Chih Hsiung.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 1025-1030 4450302 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A low offset high voltage swing rail-to-rail buffer amplifier with for LCD driver
AU - Hong, Guo Teng
AU - Shen, Chih Hsiung
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper presents a design and implementation of an output buffer for LCD Driver with rail-to-rail voltage swing using TSMC 0.35 μm 2P4M process at 5V supply. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. It performs a rail-to-rail swing range and high slew rate of 14 V / μs and 11.5 V / μs for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , One is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kQ added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits the settling times of 0.7 us for rising and 0.85 μs for falling edges with voltage swing 5V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 μs and 1.80 μs for rising and falling edges , respectively. The effective area of this buffer is only 100 × 100 μm2 with build-in offset voltage holding capacitor.
AB - This paper presents a design and implementation of an output buffer for LCD Driver with rail-to-rail voltage swing using TSMC 0.35 μm 2P4M process at 5V supply. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. It performs a rail-to-rail swing range and high slew rate of 14 V / μs and 11.5 V / μs for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , One is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kQ added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits the settling times of 0.7 us for rising and 0.85 μs for falling edges with voltage swing 5V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 μs and 1.80 μs for rising and falling edges , respectively. The effective area of this buffer is only 100 × 100 μm2 with build-in offset voltage holding capacitor.
UR - http://www.scopus.com/inward/record.url?scp=43049165493&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43049165493&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2007.4450302
DO - 10.1109/EDSSC.2007.4450302
M3 - Conference contribution
AN - SCOPUS:43049165493
SN - 1424406374
SN - 9781424406371
T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
SP - 1025
EP - 1030
BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
ER -