TY - GEN
T1 - A low offset high voltage swing rail-to-rail buffer amplifier for LCD driver
AU - Hong, Guo Teng
AU - Shen, Chih-Hsiung
PY - 2007/12/1
Y1 - 2007/12/1
N2 - The size of LCDs is getting larger in particular , it is essential to compromise the driving ability. So , source drivers with high performance , high resolution , and low power dissipation will achieve more additional value. This paper presents a design and implementation of using 10-bit multiple DAC ( Digital to Analog Converter ) for the driver , and proposes a rail-to-rail output buffer with low offset and high driving ability. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. With the H-SPICE model of TSMC 0.35μm 2P4M 3.3V / 5V process , the maximum offset is less than 2mV , and the input / output swing are nearly full swing. Besides , it also performs a rail-to-rail swing range and high slew rate of 14 V / μs and 11.5 V / μs for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , one is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kΩ added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits that the settling time are within 5μs under the max voltage swing with voltage 5V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 μs and 1.80 μs for rising and falling edges , respectively. The effective area of this buffer is only 100 × 100 μm2 with build-in offset voltage holding capacitor.
AB - The size of LCDs is getting larger in particular , it is essential to compromise the driving ability. So , source drivers with high performance , high resolution , and low power dissipation will achieve more additional value. This paper presents a design and implementation of using 10-bit multiple DAC ( Digital to Analog Converter ) for the driver , and proposes a rail-to-rail output buffer with low offset and high driving ability. We designed a class-B output buffer with offset compensation ability to reduce the nonlinearity of output voltage. With the H-SPICE model of TSMC 0.35μm 2P4M 3.3V / 5V process , the maximum offset is less than 2mV , and the input / output swing are nearly full swing. Besides , it also performs a rail-to-rail swing range and high slew rate of 14 V / μs and 11.5 V / μs for rising and falling edges under a 400 pF capacitance load. For high driving capability , two push-pull output stages are used , two frequency compensation stages are also introduced for stability , one is the miller compensation with 0.04 pF capacitance , and the other is zero compensation with 0.1 kΩ added between two push-pull output stages for stable driving under different capacitance loads. The result exhibits that the settling time are within 5μs under the max voltage swing with voltage 5V under a 400 pF capacitance load. Even under a 1000 pF capacitance load , it still has the settling time of 1.52 μs and 1.80 μs for rising and falling edges , respectively. The effective area of this buffer is only 100 × 100 μm2 with build-in offset voltage holding capacitor.
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U2 - 10.1109/EDSSC.2007.4450257
DO - 10.1109/EDSSC.2007.4450257
M3 - Conference contribution
AN - SCOPUS:43049177916
SN - 1424406374
SN - 9781424406371
T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
SP - 841
EP - 846
BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Y2 - 20 December 2007 through 22 December 2007
ER -