A loop partition technique for reducing cache bank conflict in multithreaded architecture

Chao-Chin Wu, C. Chen

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Parallel multithreaded architectures take advantage of the ability to execute more than one thread simultaneously on a single chip at low synchronisation and communication costs and high hardware resource utilisation. However, a high bandwidth cache, such as a multibank cache, is especially critical to serve memory accesses issued at the same time from different threads. To prevent bank conflicts of multibank cache from seriously degrading system performance, a loop partition method is proposed to reduce or even eliminate bank conflicts. The partition allows each thread access to certain bank modules and prevents any two from accessing the same bank module. The method neither slows down the clock rate nor increases the array subscript expression complexity. The performance gains of the bank-conflict-free loop partition approach are shown in simulation results.

Original languageEnglish
Pages (from-to)30-36
Number of pages7
JournalIEE Proceedings: Computers and Digital Techniques
Volume143
Issue number1
DOIs
Publication statusPublished - 1996 Jan 1

Fingerprint

Parallel architectures
Cache
Clocks
Synchronization
Partition
Hardware
Bandwidth
Data storage equipment
Thread
Communication
Costs
Subscript
Module
Parallel Architectures
Communication Cost
System Performance
Chip
Eliminate
Banks
Architecture

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

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A loop partition technique for reducing cache bank conflict in multithreaded architecture. / Wu, Chao-Chin; Chen, C.

In: IEE Proceedings: Computers and Digital Techniques, Vol. 143, No. 1, 01.01.1996, p. 30-36.

Research output: Contribution to journalArticle

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