A loop optimization technique for speculative chip multiprocessors

Chao Chin Wu, Kuan Chou Lai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.

Original languageEnglish
Title of host publicationProceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06
Pages55-56
Number of pages2
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 International Workshop on Networking, Architecture, and Storages, NAS'06 - Shenyang, China
Duration: 2006 Aug 12006 Aug 3

Publication series

NameProceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06
Volume2006

Other

Other2006 International Workshop on Networking, Architecture, and Storages, NAS'06
CountryChina
CityShenyang
Period06-08-0106-08-03

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Wu, C. C., & Lai, K. C. (2006). A loop optimization technique for speculative chip multiprocessors. In Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06 (pp. 55-56). [1654530] (Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06; Vol. 2006). https://doi.org/10.1109/IWNAS.2006.9