A loop optimization technique for speculative chip multiprocessors

Chao Chin Wu, Kuan Chou Lai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.

Original languageEnglish
Title of host publicationProceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06
Pages55-56
Number of pages2
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 International Workshop on Networking, Architecture, and Storages, NAS'06 - Shenyang, China
Duration: 2006 Aug 12006 Aug 3

Publication series

NameProceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06
Volume2006

Other

Other2006 International Workshop on Networking, Architecture, and Storages, NAS'06
CountryChina
CityShenyang
Period06-08-0106-08-03

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Wu, C. C., & Lai, K. C. (2006). A loop optimization technique for speculative chip multiprocessors. In Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06 (pp. 55-56). [1654530] (Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06; Vol. 2006). https://doi.org/10.1109/IWNAS.2006.9
Wu, Chao Chin ; Lai, Kuan Chou. / A loop optimization technique for speculative chip multiprocessors. Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06. 2006. pp. 55-56 (Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06).
@inproceedings{148ad787a6b1495dbe97b2d2e6bb93e5,
title = "A loop optimization technique for speculative chip multiprocessors",
abstract = "According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.",
author = "Wu, {Chao Chin} and Lai, {Kuan Chou}",
year = "2006",
month = "12",
day = "1",
doi = "10.1109/IWNAS.2006.9",
language = "English",
isbn = "0769526519",
series = "Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06",
pages = "55--56",
booktitle = "Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06",

}

Wu, CC & Lai, KC 2006, A loop optimization technique for speculative chip multiprocessors. in Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06., 1654530, Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06, vol. 2006, pp. 55-56, 2006 International Workshop on Networking, Architecture, and Storages, NAS'06, Shenyang, China, 06-08-01. https://doi.org/10.1109/IWNAS.2006.9

A loop optimization technique for speculative chip multiprocessors. / Wu, Chao Chin; Lai, Kuan Chou.

Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06. 2006. p. 55-56 1654530 (Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A loop optimization technique for speculative chip multiprocessors

AU - Wu, Chao Chin

AU - Lai, Kuan Chou

PY - 2006/12/1

Y1 - 2006/12/1

N2 - According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.

AB - According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.

UR - http://www.scopus.com/inward/record.url?scp=34247253097&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34247253097&partnerID=8YFLogxK

U2 - 10.1109/IWNAS.2006.9

DO - 10.1109/IWNAS.2006.9

M3 - Conference contribution

AN - SCOPUS:34247253097

SN - 0769526519

SN - 9780769526515

T3 - Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06

SP - 55

EP - 56

BT - Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06

ER -

Wu CC, Lai KC. A loop optimization technique for speculative chip multiprocessors. In Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06. 2006. p. 55-56. 1654530. (Proceedings - 2006 International Workshop on Networking, Architecture, and Storages, NAS'06). https://doi.org/10.1109/IWNAS.2006.9