A hybrid LFSR design for low power applications

Tsung Chu Huang, Kuen Jong Lee

Research output: Contribution to journalArticle

Abstract

Linear feedback shift registers are commonly used in many fields, such as in built-in self-testing (BIST), compression, and communication. A parallel implementation of an n-stage LFSR using an n-phase clocking scheme has been proposed to reduce the data transitions during test and signal processes; however, due to the more complex clock generator, broadcasting input, and demultiplexing output, the power reduction of previous work is actually quite limited. This paper improves the power reduction by developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator, as well as employing static logic gates to implement the output demultiplexer. To reduce the stages of the multiphase clock generator and the area of the demultiplexer, a hybrid LFSR design combining both single and multiple phase clocks has been developed. From our evaluation based on a transition model (taking into account the power dissipation due to the clock tree, the broadcasting input and the demultiplexing output, when n is greater than 28), our architecture has 40% more power reduction than the previous n-phase LFSR architecture, and up to 70% power reduction compared to a conventional LFSR.

Original languageEnglish
Pages (from-to)1-9
Number of pages9
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume10
Issue number1
Publication statusPublished - 2003 Feb 1

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Clocks
Demultiplexing
Broadcasting
Compression testing
Shift registers
Logic gates
Energy dissipation
Feedback
Communication
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{7352a9116c0d4123898c73094eab90a6,
title = "A hybrid LFSR design for low power applications",
abstract = "Linear feedback shift registers are commonly used in many fields, such as in built-in self-testing (BIST), compression, and communication. A parallel implementation of an n-stage LFSR using an n-phase clocking scheme has been proposed to reduce the data transitions during test and signal processes; however, due to the more complex clock generator, broadcasting input, and demultiplexing output, the power reduction of previous work is actually quite limited. This paper improves the power reduction by developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator, as well as employing static logic gates to implement the output demultiplexer. To reduce the stages of the multiphase clock generator and the area of the demultiplexer, a hybrid LFSR design combining both single and multiple phase clocks has been developed. From our evaluation based on a transition model (taking into account the power dissipation due to the clock tree, the broadcasting input and the demultiplexing output, when n is greater than 28), our architecture has 40{\%} more power reduction than the previous n-phase LFSR architecture, and up to 70{\%} power reduction compared to a conventional LFSR.",
author = "Huang, {Tsung Chu} and Lee, {Kuen Jong}",
year = "2003",
month = "2",
day = "1",
language = "English",
volume = "10",
pages = "1--9",
journal = "International Journal of Electrical Engineering",
issn = "1812-3031",
publisher = "Chinese Institute of Electrical Engineering",
number = "1",

}

TY - JOUR

T1 - A hybrid LFSR design for low power applications

AU - Huang, Tsung Chu

AU - Lee, Kuen Jong

PY - 2003/2/1

Y1 - 2003/2/1

N2 - Linear feedback shift registers are commonly used in many fields, such as in built-in self-testing (BIST), compression, and communication. A parallel implementation of an n-stage LFSR using an n-phase clocking scheme has been proposed to reduce the data transitions during test and signal processes; however, due to the more complex clock generator, broadcasting input, and demultiplexing output, the power reduction of previous work is actually quite limited. This paper improves the power reduction by developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator, as well as employing static logic gates to implement the output demultiplexer. To reduce the stages of the multiphase clock generator and the area of the demultiplexer, a hybrid LFSR design combining both single and multiple phase clocks has been developed. From our evaluation based on a transition model (taking into account the power dissipation due to the clock tree, the broadcasting input and the demultiplexing output, when n is greater than 28), our architecture has 40% more power reduction than the previous n-phase LFSR architecture, and up to 70% power reduction compared to a conventional LFSR.

AB - Linear feedback shift registers are commonly used in many fields, such as in built-in self-testing (BIST), compression, and communication. A parallel implementation of an n-stage LFSR using an n-phase clocking scheme has been proposed to reduce the data transitions during test and signal processes; however, due to the more complex clock generator, broadcasting input, and demultiplexing output, the power reduction of previous work is actually quite limited. This paper improves the power reduction by developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator, as well as employing static logic gates to implement the output demultiplexer. To reduce the stages of the multiphase clock generator and the area of the demultiplexer, a hybrid LFSR design combining both single and multiple phase clocks has been developed. From our evaluation based on a transition model (taking into account the power dissipation due to the clock tree, the broadcasting input and the demultiplexing output, when n is greater than 28), our architecture has 40% more power reduction than the previous n-phase LFSR architecture, and up to 70% power reduction compared to a conventional LFSR.

UR - http://www.scopus.com/inward/record.url?scp=0037332302&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0037332302&partnerID=8YFLogxK

M3 - Article

VL - 10

SP - 1

EP - 9

JO - International Journal of Electrical Engineering

JF - International Journal of Electrical Engineering

SN - 1812-3031

IS - 1

ER -