Light-weight network gateways often employ a cost-effective embedded network processor and have received a strong demand for empowering content filtering services. In this regard, we were motivated to propose a specialized cache, fuzzy-updated cache automata matching (FCAM) circuit for accelerating the embedded network processors. Although automata matching algorithms are robust with deterministic matching time, there is still plenty of room for improving its average-case performance. The proposed FCAM employs cache to accelerate the root state and nonroot state with the multiple characters matching, and applies the fuzzy decision to improve the cache performance. In our experiment, the FPGA implementation of FCAM can perform at the rate of 10.5 Giga bits per second with the patterns of 25,642 bytes. This performance is superior to previous matching hardware in terms of throughput and pattern set.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering