A fuzzy-updated cache of automata matching for embedded network processor

Kuo Kun Tseng, Yeong Lin Lai, Chin Cheng Chen, Chih Yu Hsu

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Light-weight network gateways often employ a cost-effective embedded network processor and have received a strong demand for empowering content filtering services. In this regard, we were motivated to propose a specialized cache, fuzzy-updated cache automata matching (FCAM) circuit for accelerating the embedded network processors. Although automata matching algorithms are robust with deterministic matching time, there is still plenty of room for improving its average-case performance. The proposed FCAM employs cache to accelerate the root state and nonroot state with the multiple characters matching, and applies the fuzzy decision to improve the cache performance. In our experiment, the FPGA implementation of FCAM can perform at the rate of 10.5 Giga bits per second with the patterns of 25,642 bytes. This performance is superior to previous matching hardware in terms of throughput and pattern set.

Original languageEnglish
Pages (from-to)401-415
Number of pages15
JournalJournal of Circuits, Systems and Computers
Volume20
Issue number3
DOIs
Publication statusPublished - 2011 May 1

Fingerprint

Field programmable gate arrays (FPGA)
Throughput
Hardware
Networks (circuits)
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Tseng, Kuo Kun ; Lai, Yeong Lin ; Chen, Chin Cheng ; Hsu, Chih Yu. / A fuzzy-updated cache of automata matching for embedded network processor. In: Journal of Circuits, Systems and Computers. 2011 ; Vol. 20, No. 3. pp. 401-415.
@article{a0aaf9d292bf443bb0659d7623dfecf8,
title = "A fuzzy-updated cache of automata matching for embedded network processor",
abstract = "Light-weight network gateways often employ a cost-effective embedded network processor and have received a strong demand for empowering content filtering services. In this regard, we were motivated to propose a specialized cache, fuzzy-updated cache automata matching (FCAM) circuit for accelerating the embedded network processors. Although automata matching algorithms are robust with deterministic matching time, there is still plenty of room for improving its average-case performance. The proposed FCAM employs cache to accelerate the root state and nonroot state with the multiple characters matching, and applies the fuzzy decision to improve the cache performance. In our experiment, the FPGA implementation of FCAM can perform at the rate of 10.5 Giga bits per second with the patterns of 25,642 bytes. This performance is superior to previous matching hardware in terms of throughput and pattern set.",
author = "Tseng, {Kuo Kun} and Lai, {Yeong Lin} and Chen, {Chin Cheng} and Hsu, {Chih Yu}",
year = "2011",
month = "5",
day = "1",
doi = "10.1142/S0218126611007360",
language = "English",
volume = "20",
pages = "401--415",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "3",

}

A fuzzy-updated cache of automata matching for embedded network processor. / Tseng, Kuo Kun; Lai, Yeong Lin; Chen, Chin Cheng; Hsu, Chih Yu.

In: Journal of Circuits, Systems and Computers, Vol. 20, No. 3, 01.05.2011, p. 401-415.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A fuzzy-updated cache of automata matching for embedded network processor

AU - Tseng, Kuo Kun

AU - Lai, Yeong Lin

AU - Chen, Chin Cheng

AU - Hsu, Chih Yu

PY - 2011/5/1

Y1 - 2011/5/1

N2 - Light-weight network gateways often employ a cost-effective embedded network processor and have received a strong demand for empowering content filtering services. In this regard, we were motivated to propose a specialized cache, fuzzy-updated cache automata matching (FCAM) circuit for accelerating the embedded network processors. Although automata matching algorithms are robust with deterministic matching time, there is still plenty of room for improving its average-case performance. The proposed FCAM employs cache to accelerate the root state and nonroot state with the multiple characters matching, and applies the fuzzy decision to improve the cache performance. In our experiment, the FPGA implementation of FCAM can perform at the rate of 10.5 Giga bits per second with the patterns of 25,642 bytes. This performance is superior to previous matching hardware in terms of throughput and pattern set.

AB - Light-weight network gateways often employ a cost-effective embedded network processor and have received a strong demand for empowering content filtering services. In this regard, we were motivated to propose a specialized cache, fuzzy-updated cache automata matching (FCAM) circuit for accelerating the embedded network processors. Although automata matching algorithms are robust with deterministic matching time, there is still plenty of room for improving its average-case performance. The proposed FCAM employs cache to accelerate the root state and nonroot state with the multiple characters matching, and applies the fuzzy decision to improve the cache performance. In our experiment, the FPGA implementation of FCAM can perform at the rate of 10.5 Giga bits per second with the patterns of 25,642 bytes. This performance is superior to previous matching hardware in terms of throughput and pattern set.

UR - http://www.scopus.com/inward/record.url?scp=79954468730&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79954468730&partnerID=8YFLogxK

U2 - 10.1142/S0218126611007360

DO - 10.1142/S0218126611007360

M3 - Article

AN - SCOPUS:79954468730

VL - 20

SP - 401

EP - 415

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 3

ER -