A fast probability-based algorithm for leakage current reduction considering controller cost

Tsung Yi Wu; Jr Luen Tzeng; Kuang Yao Chen

doi:10.1109/ASPDAC.2007.358064

A fast probability-based algorithm for leakage current reduction considering controller cost

Tsung Yi Wu, Jr Luen Tzeng, Kuang Yao Chen

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages	672-677
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2007.358064
Publication status	Published - 2007 Dec 1
Event	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan Duration: 2007 Jan 23 → 2007 Jan 27

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Country	Japan
City	Yokohama
Period	07-01-23 → 07-01-27

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2007.358064

Fingerprint Dive into the research topics of 'A fast probability-based algorithm for leakage current reduction considering controller cost'. Together they form a unique fingerprint.

Cite this

Wu, T. Y., Tzeng, J. L., & Chen, K. Y. (2007). A fast probability-based algorithm for leakage current reduction considering controller cost. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 672-677). [4196110] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.358064

@inproceedings{0be4d4bff76e4bd68d218bd1ec2767c2,

title = "A fast probability-based algorithm for leakage current reduction considering controller cost",

abstract = "Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.",

author = "Wu, {Tsung Yi} and Tzeng, {Jr Luen} and Chen, {Kuang Yao}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/ASPDAC.2007.358064",

language = "English",

isbn = "1424406293",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "672--677",

booktitle = "Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007",

note = "ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 ; Conference date: 23-01-2007 Through 27-01-2007",

}

Wu, TY, Tzeng, JL & Chen, KY 2007, A fast probability-based algorithm for leakage current reduction considering controller cost. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196110, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 672-677, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 07-01-23. https://doi.org/10.1109/ASPDAC.2007.358064

A fast probability-based algorithm for leakage current reduction considering controller cost. / Wu, Tsung Yi; Tzeng, Jr Luen; Chen, Kuang Yao.

Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 672-677 4196110 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A fast probability-based algorithm for leakage current reduction considering controller cost

AU - Wu, Tsung Yi

AU - Tzeng, Jr Luen

AU - Chen, Kuang Yao

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

AB - Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

UR - http://www.scopus.com/inward/record.url?scp=46649105073&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46649105073&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2007.358064

DO - 10.1109/ASPDAC.2007.358064

M3 - Conference contribution

AN - SCOPUS:46649105073

SN - 1424406293

SN - 9781424406296

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 672

EP - 677

BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

Y2 - 23 January 2007 through 27 January 2007

ER -