A fast probability-based algorithm for leakage current reduction considering controller cost

Tsung-Yi Wu, Jr Luen Tzeng, Kuang Yao Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages672-677
Number of pages6
DOIs
Publication statusPublished - 2007 Dec 1
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: 2007 Jan 232007 Jan 27

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period07-01-2307-01-27

Fingerprint

Leakage currents
Controllers
Costs
Logic gates
Networks (circuits)
Flip flop circuits
Digital circuits

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Wu, T-Y., Tzeng, J. L., & Chen, K. Y. (2007). A fast probability-based algorithm for leakage current reduction considering controller cost. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 672-677). [4196110] https://doi.org/10.1109/ASPDAC.2007.358064
Wu, Tsung-Yi ; Tzeng, Jr Luen ; Chen, Kuang Yao. / A fast probability-based algorithm for leakage current reduction considering controller cost. Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. pp. 672-677
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abstract = "Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48{\%} and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.",
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Wu, T-Y, Tzeng, JL & Chen, KY 2007, A fast probability-based algorithm for leakage current reduction considering controller cost. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196110, pp. 672-677, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 07-01-23. https://doi.org/10.1109/ASPDAC.2007.358064

A fast probability-based algorithm for leakage current reduction considering controller cost. / Wu, Tsung-Yi; Tzeng, Jr Luen; Chen, Kuang Yao.

Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 672-677 4196110.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

AB - Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

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Wu T-Y, Tzeng JL, Chen KY. A fast probability-based algorithm for leakage current reduction considering controller cost. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 672-677. 4196110 https://doi.org/10.1109/ASPDAC.2007.358064