A dynamically clustered chip multiprocessor

Chao Chin Wu; Guan Joe Lai

doi:10.1109/PACRIM.2005.1517238

A dynamically clustered chip multiprocessor

Chao Chin Wu, Guan Joe Lai

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.

Original language	English
Title of host publication	2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM - Proceedings
Pages	113-116
Number of pages	4
DOIs	https://doi.org/10.1109/PACRIM.2005.1517238
Publication status	Published - 2005 Dec 1
Event	2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM - Victoria, BC, Canada Duration: 2005 Aug 24 → 2005 Aug 26

Publication series

Name	IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings
Volume	2005

Other

Other	2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM
Country	Canada
City	Victoria, BC
Period	05-08-24 → 05-08-26

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All Science Journal Classification (ASJC) codes

Signal Processing
Computer Networks and Communications

Cite this

Wu, C. C., & Lai, G. J. (2005). A dynamically clustered chip multiprocessor. In 2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM - Proceedings (pp. 113-116). [1517238] (IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings; Vol. 2005). https://doi.org/10.1109/PACRIM.2005.1517238

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abstract = "Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.",

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Wu, CC & Lai, GJ 2005, A dynamically clustered chip multiprocessor. in 2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM - Proceedings., 1517238, IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings, vol. 2005, pp. 113-116, 2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM, Victoria, BC, Canada, 05-08-24. https://doi.org/10.1109/PACRIM.2005.1517238

A dynamically clustered chip multiprocessor. / Wu, Chao Chin; Lai, Guan Joe.

2005 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing, PACRIM - Proceedings. 2005. p. 113-116 1517238 (IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.

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Access to Document

10.1109/PACRIM.2005.1517238