An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs. The proposed DDFS was implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification. The spurious-free dynamic range (SFDR) measured from FPGA board is about 84 dBc on average. The TSMC 0.18μm technology is adopted in the cell-based library implementation. The simulated power efficiency is 0.041 mW/MHz averaged for 0.18μm technology. The gate count is about 5384 calculated using the design compiler. The maximum clock frequency can reach to 225 MHz.
|Number of pages||5|
|Journal||AEU - International Journal of Electronics and Communications|
|Publication status||Published - 2010 Nov 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering