In this paper, we present a transistor placement methodology for CMOS analog integrated circuit that leads the subsequent phase to conform to analog layout constraints, such as: matching, symmetry, signal coupling and geometric constraints such as: cell aspect ratio (or cell height), and user-defined cell input/output pin locations. This placement methodology bases on the characteristics of current-paths and the layout constraints can help us to obtain better performance, that is guaranteed by experimental results.
|Title of host publication||Advances in Physics, Electronics and Signal Processing Applications|
|Publisher||World Scientific and Engineering Academy and Society|
|Number of pages||4|
|Publication status||Published - 2000 Dec 1|
All Science Journal Classification (ASJC) codes