Abstract
In this paper, we present a transistor placement methodology for CMOS analog integrated circuit that leads the subsequent phase to conform to analog layout constraints, such as: matching, symmetry, signal coupling and geometric constraints such as: cell aspect ratio (or cell height), and user-defined cell input/output pin locations. This placement methodology bases on the characteristics of current-paths and the layout constraints can help us to obtain better performance, that is guaranteed by experimental results.
| Original language | English |
|---|---|
| Title of host publication | Advances in Physics, Electronics and Signal Processing Applications |
| Publisher | World Scientific and Engineering Academy and Society |
| Pages | 94-97 |
| Number of pages | 4 |
| ISBN (Print) | 9608052173 |
| Publication status | Published - 2000 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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A current-path based placement methodology for analog IC layout design. / Lin, Zhi Ming; Liao, Mei Yuan; Huang, Kuei Chen.
Advances in Physics, Electronics and Signal Processing Applications. World Scientific and Engineering Academy and Society, 2000. p. 94-97.Research output: Chapter in Book/Report/Conference proceeding › Chapter
TY - CHAP
T1 - A current-path based placement methodology for analog IC layout design
AU - Lin, Zhi Ming
AU - Liao, Mei Yuan
AU - Huang, Kuei Chen
PY - 2000/12/1
Y1 - 2000/12/1
N2 - In this paper, we present a transistor placement methodology for CMOS analog integrated circuit that leads the subsequent phase to conform to analog layout constraints, such as: matching, symmetry, signal coupling and geometric constraints such as: cell aspect ratio (or cell height), and user-defined cell input/output pin locations. This placement methodology bases on the characteristics of current-paths and the layout constraints can help us to obtain better performance, that is guaranteed by experimental results.
AB - In this paper, we present a transistor placement methodology for CMOS analog integrated circuit that leads the subsequent phase to conform to analog layout constraints, such as: matching, symmetry, signal coupling and geometric constraints such as: cell aspect ratio (or cell height), and user-defined cell input/output pin locations. This placement methodology bases on the characteristics of current-paths and the layout constraints can help us to obtain better performance, that is guaranteed by experimental results.
UR - http://www.scopus.com/inward/record.url?scp=4944225486&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=4944225486&partnerID=8YFLogxK
M3 - Chapter
AN - SCOPUS:4944225486
SN - 9608052173
SP - 94
EP - 97
BT - Advances in Physics, Electronics and Signal Processing Applications
PB - World Scientific and Engineering Academy and Society
ER -