A current-path based placement methodology for analog IC layout design

Zhi Ming Lin; Mei Yuan Liao; Kuei Chen Huang

A current-path based placement methodology for analog IC layout design

Zhi Ming Lin, Mei Yuan Liao, Kuei Chen Huang

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In this paper, we present a transistor placement methodology for CMOS analog integrated circuit that leads the subsequent phase to conform to analog layout constraints, such as: matching, symmetry, signal coupling and geometric constraints such as: cell aspect ratio (or cell height), and user-defined cell input/output pin locations. This placement methodology bases on the characteristics of current-paths and the layout constraints can help us to obtain better performance, that is guaranteed by experimental results.

Original language	English
Title of host publication	Advances in Physics, Electronics and Signal Processing Applications
Publisher	World Scientific and Engineering Academy and Society
Pages	94-97
Number of pages	4
ISBN (Print)	9608052173
Publication status	Published - 2000 Dec 1

All Science Journal Classification (ASJC) codes

Engineering(all)

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