Abstract
A new conditional isolation technique (CI-Domino) in domino logic is proposed for wide domino gates. This technique can not only reduce the subthreshold and gate oxide leakage currents simultaneously without sacrificing circuit performance, but also it can be utilized to speed up the evaluation time of domino gate. Simulations on high fanin domino OR gates with 0.18 μm process technology show that the proposed technique achieves reduction on total static power by 36%, dynamic power by 49.14%, and delay time by 60.27% compared to the conventional domino gate. Meanwhile, the proposed technique also gains about 48.14% improvement on leakage tolerance.
| Original language | English |
|---|---|
| Pages (from-to) | 386-390 |
| Number of pages | 5 |
| Journal | IEICE Transactions on Electronics |
| Volume | E92-C |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2009 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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A conditional isolation technique for low-energy and high-performance wide domino gates. / Lin, How Rern; Chiu, Wei Hao; Wu, Tsung-Yi.
In: IEICE Transactions on Electronics, Vol. E92-C, No. 4, 01.01.2009, p. 386-390.Research output: Contribution to journal › Article
TY - JOUR
T1 - A conditional isolation technique for low-energy and high-performance wide domino gates
AU - Lin, How Rern
AU - Chiu, Wei Hao
AU - Wu, Tsung-Yi
PY - 2009/1/1
Y1 - 2009/1/1
N2 - A new conditional isolation technique (CI-Domino) in domino logic is proposed for wide domino gates. This technique can not only reduce the subthreshold and gate oxide leakage currents simultaneously without sacrificing circuit performance, but also it can be utilized to speed up the evaluation time of domino gate. Simulations on high fanin domino OR gates with 0.18 μm process technology show that the proposed technique achieves reduction on total static power by 36%, dynamic power by 49.14%, and delay time by 60.27% compared to the conventional domino gate. Meanwhile, the proposed technique also gains about 48.14% improvement on leakage tolerance.
AB - A new conditional isolation technique (CI-Domino) in domino logic is proposed for wide domino gates. This technique can not only reduce the subthreshold and gate oxide leakage currents simultaneously without sacrificing circuit performance, but also it can be utilized to speed up the evaluation time of domino gate. Simulations on high fanin domino OR gates with 0.18 μm process technology show that the proposed technique achieves reduction on total static power by 36%, dynamic power by 49.14%, and delay time by 60.27% compared to the conventional domino gate. Meanwhile, the proposed technique also gains about 48.14% improvement on leakage tolerance.
UR - http://www.scopus.com/inward/record.url?scp=77950429611&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950429611&partnerID=8YFLogxK
U2 - 10.1587/transele.E92.C.386
DO - 10.1587/transele.E92.C.386
M3 - Article
AN - SCOPUS:77950429611
VL - E92-C
SP - 386
EP - 390
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 4
ER -