A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC

Yi Cheng Chen; Jyun Syong Lai; Zhi Ming Lin

doi:10.1109/EDSSC.2013.6628099

A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC

Yi Cheng Chen, Jyun Syong Lai, Zhi Ming Lin

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

Original language	English
Title of host publication	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs	https://doi.org/10.1109/EDSSC.2013.6628099
Publication status	Published - 2013 Dec 23
Event	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong Duration: 2013 Jun 3 → 2013 Jun 5

Other

Other	2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
Country	Hong Kong
City	Hong Kong
Period	13-06-03 → 13-06-05

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2013.6628099

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Cite this

@inproceedings{7f6f152b0d9f4639ab846318586b35b0,

title = "A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC",

abstract = "In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.",

author = "Chen, {Yi Cheng} and Lai, {Jyun Syong} and Lin, {Zhi Ming}",

year = "2013",

month = dec,

day = "23",

doi = "10.1109/EDSSC.2013.6628099",

language = "English",

isbn = "9781467325233",

booktitle = "2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013",

note = "2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 ; Conference date: 03-06-2013 Through 05-06-2013",

}

Chen, YC, Lai, JS & Lin, ZM 2013, A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. in 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013., 6628099, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, Hong Kong, Hong Kong, 13-06-03. https://doi.org/10.1109/EDSSC.2013.6628099

TY - GEN

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AU - Chen, Yi Cheng

AU - Lai, Jyun Syong

AU - Lin, Zhi Ming

PY - 2013/12/23

Y1 - 2013/12/23

N2 - In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

AB - In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

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DO - 10.1109/EDSSC.2013.6628099

M3 - Conference contribution

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SN - 9781467325233

BT - 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

T2 - 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

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