Abstract
In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.
| Original language | English |
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| Title of host publication | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 |
| DOIs | |
| Publication status | Published - 2013 Dec 23 |
| Event | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong Duration: 2013 Jun 3 → 2013 Jun 5 |
Other
| Other | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 |
|---|---|
| Country | Hong Kong |
| City | Hong Kong |
| Period | 13-06-03 → 13-06-05 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
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Cite this
Chen, Y. C., Lai, J. S., & Lin, Z. M. (2013). A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628099] https://doi.org/10.1109/EDSSC.2013.6628099