A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC

Yi Cheng Chen, Jyun Syong Lai, Zhi Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
Publication statusPublished - 2013 Dec 23
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
Duration: 2013 Jun 32013 Jun 5

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CountryHong Kong
CityHong Kong
Period13-06-0313-06-05

Fingerprint

Digital to analog conversion
Networks (circuits)
Binary codes
Thermometers
Energy dissipation
Transistors

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chen, Y. C., Lai, J. S., & Lin, Z. M. (2013). A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628099] https://doi.org/10.1109/EDSSC.2013.6628099
Chen, Yi Cheng ; Lai, Jyun Syong ; Lin, Zhi Ming. / A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013.
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abstract = "In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.",
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Chen, YC, Lai, JS & Lin, ZM 2013, A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. in 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013., 6628099, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, Hong Kong, Hong Kong, 13-06-03. https://doi.org/10.1109/EDSSC.2013.6628099

A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. / Chen, Yi Cheng; Lai, Jyun Syong; Lin, Zhi Ming.

2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628099.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

AB - In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

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Chen YC, Lai JS, Lin ZM. A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 2013. 6628099 https://doi.org/10.1109/EDSSC.2013.6628099