A 6-bit 2GS/s low power flash ADC

Jyun Syong Lai, Zhi-Ming Lin

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.

Original languageEnglish
Pages369-371
Number of pages3
Publication statusPublished - 2012 Jan 1
Event2012 International Workshop on Computer Science and Engineering, WCSE 2012 - Hong Kong, Hong Kong
Duration: 2012 Aug 32012 Aug 4

Conference

Conference2012 International Workshop on Computer Science and Engineering, WCSE 2012
CountryHong Kong
CityHong Kong
Period12-08-0312-08-04

Fingerprint

Digital to analog conversion
Resistors
Transistors
Electric power utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)

Cite this

Lai, J. S., & Lin, Z-M. (2012). A 6-bit 2GS/s low power flash ADC. 369-371. Paper presented at 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong.
Lai, Jyun Syong ; Lin, Zhi-Ming. / A 6-bit 2GS/s low power flash ADC. Paper presented at 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong.3 p.
@conference{7db9b8c0e6b546f9a0e6d3bd4ed1d032,
title = "A 6-bit 2GS/s low power flash ADC",
abstract = "In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.",
author = "Lai, {Jyun Syong} and Zhi-Ming Lin",
year = "2012",
month = "1",
day = "1",
language = "English",
pages = "369--371",
note = "2012 International Workshop on Computer Science and Engineering, WCSE 2012 ; Conference date: 03-08-2012 Through 04-08-2012",

}

Lai, JS & Lin, Z-M 2012, 'A 6-bit 2GS/s low power flash ADC', Paper presented at 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong, 12-08-03 - 12-08-04 pp. 369-371.

A 6-bit 2GS/s low power flash ADC. / Lai, Jyun Syong; Lin, Zhi-Ming.

2012. 369-371 Paper presented at 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong.

Research output: Contribution to conferencePaper

TY - CONF

T1 - A 6-bit 2GS/s low power flash ADC

AU - Lai, Jyun Syong

AU - Lin, Zhi-Ming

PY - 2012/1/1

Y1 - 2012/1/1

N2 - In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.

AB - In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85064096469&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85064096469&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:85064096469

SP - 369

EP - 371

ER -

Lai JS, Lin Z-M. A 6-bit 2GS/s low power flash ADC. 2012. Paper presented at 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong.