Abstract
In this paper, a 5.8 GHz fully-integrated power amplifier is designed and implemented in a 0.18-μm radio frequency CMOS process. The power amplifier is formed by a cascaded class-D pre-amplifier and a class-E amplifier to drive the output power stage. The designed PA delivered an output power of 13.86 dBm with a power-added efficiency (PAE) of 20% and a power gain of 26.66 dB.
| Original language | English |
|---|---|
| Title of host publication | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
| Pages | 1012-1016 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 2007 Dec 1 |
| Event | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 2007 Dec 20 → 2007 Dec 22 |
Publication series
| Name | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|
Other
| Other | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|---|
| Country | Taiwan |
| City | Tainan |
| Period | 07-12-20 → 07-12-22 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
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A 5.8 GHz fully-integrated power amplifier for 802.11a WLAN system. / Lin, G. C.; Lin, Zhi-Ming.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 1012-1016 4450299 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 5.8 GHz fully-integrated power amplifier for 802.11a WLAN system
AU - Lin, G. C.
AU - Lin, Zhi-Ming
PY - 2007/12/1
Y1 - 2007/12/1
N2 - In this paper, a 5.8 GHz fully-integrated power amplifier is designed and implemented in a 0.18-μm radio frequency CMOS process. The power amplifier is formed by a cascaded class-D pre-amplifier and a class-E amplifier to drive the output power stage. The designed PA delivered an output power of 13.86 dBm with a power-added efficiency (PAE) of 20% and a power gain of 26.66 dB.
AB - In this paper, a 5.8 GHz fully-integrated power amplifier is designed and implemented in a 0.18-μm radio frequency CMOS process. The power amplifier is formed by a cascaded class-D pre-amplifier and a class-E amplifier to drive the output power stage. The designed PA delivered an output power of 13.86 dBm with a power-added efficiency (PAE) of 20% and a power gain of 26.66 dB.
UR - http://www.scopus.com/inward/record.url?scp=43049157706&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43049157706&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2007.4450299
DO - 10.1109/EDSSC.2007.4450299
M3 - Conference contribution
AN - SCOPUS:43049157706
SN - 1424406374
SN - 9781424406371
T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
SP - 1012
EP - 1016
BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
ER -