A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies

Chien Ping Chou, Zhi-Ming Lin, Jun Da Chen

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Abstract

This paper proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35- μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid U P and DOWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.

Original languageEnglish
Pages937-940
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

Fingerprint

Detectors
State feedback
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chou, C. P., Lin, Z-M., & Chen, J. D. (2004). A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies. 937-940. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Chou, Chien Ping ; Lin, Zhi-Ming ; Chen, Jun Da. / A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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Chou, CP, Lin, Z-M & Chen, JD 2004, 'A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies', Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 pp. 937-940.

A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies. / Chou, Chien Ping; Lin, Zhi-Ming; Chen, Jun Da.

2004. 937-940 Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

Research output: Contribution to conferencePaper

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AB - This paper proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35- μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid U P and DOWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.

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Chou CP, Lin Z-M, Chen JD. A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies. 2004. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.