Abstract
This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.
| Original language | English |
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| Title of host publication | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
| Pages | 881-884 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2007 Dec 1 |
| Event | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 2007 Dec 20 → 2007 Dec 22 |
Publication series
| Name | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|
Other
| Other | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 |
|---|---|
| Country | Taiwan |
| City | Tainan |
| Period | 07-12-20 → 07-12-22 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
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Cite this
Hsu, T. Y., & Lin, Z-M. (2007). A 12 bit direct level-signal transition based pipelined analog-to-digital converter. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (pp. 881-884). [4450266] (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450266