TY - GEN
T1 - A 12 bit direct level-signal transition based pipelined analog-to-digital converter
AU - Hsu, T. Y.
AU - Lin, Zhi-Ming
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.
AB - This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.
UR - http://www.scopus.com/inward/record.url?scp=43049179542&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43049179542&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2007.4450266
DO - 10.1109/EDSSC.2007.4450266
M3 - Conference contribution
AN - SCOPUS:43049179542
SN - 1424406374
SN - 9781424406371
T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
SP - 881
EP - 884
BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Y2 - 20 December 2007 through 22 December 2007
ER -