A 12 bit direct level-signal transition based pipelined analog-to-digital converter

T. Y. Hsu; Zhi-Ming Lin

doi:10.1109/EDSSC.2007.4450266

A 12 bit direct level-signal transition based pipelined analog-to-digital converter

T. Y. Hsu, Zhi-Ming Lin

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	881-884
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450266
Publication status	Published - 2007 Dec 1
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 2007 Dec 20 → 2007 Dec 22

Publication series

Name	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Country	Taiwan
City	Tainan
Period	07-12-20 → 07-12-22

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EDSSC.2007.4450266

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title = "A 12 bit direct level-signal transition based pipelined analog-to-digital converter",

abstract = "This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.",

author = "Hsu, {T. Y.} and Zhi-Ming Lin",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/EDSSC.2007.4450266",

language = "English",

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series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "881--884",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Hsu, TY & Lin, Z-M 2007, A 12 bit direct level-signal transition based pipelined analog-to-digital converter. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450266, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 881-884, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 07-12-20. https://doi.org/10.1109/EDSSC.2007.4450266

A 12 bit direct level-signal transition based pipelined analog-to-digital converter. / Hsu, T. Y.; Lin, Zhi-Ming.

IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 881-884 4450266 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

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