A 12 bit direct level-signal transition based pipelined analog-to-digital converter

T. Y. Hsu, Zhi-Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

Original languageEnglish
Title of host publicationIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages881-884
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
EventIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan
Duration: 2007 Dec 202007 Dec 22

Publication series

NameIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
CountryTaiwan
CityTainan
Period07-12-2007-12-22

Fingerprint

Digital to analog conversion
Transistors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Hsu, T. Y., & Lin, Z-M. (2007). A 12 bit direct level-signal transition based pipelined analog-to-digital converter. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (pp. 881-884). [4450266] (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450266
Hsu, T. Y. ; Lin, Zhi-Ming. / A 12 bit direct level-signal transition based pipelined analog-to-digital converter. IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. pp. 881-884 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).
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abstract = "This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80{\%} of transistor numbers.",
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Hsu, TY & Lin, Z-M 2007, A 12 bit direct level-signal transition based pipelined analog-to-digital converter. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450266, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 881-884, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 07-12-20. https://doi.org/10.1109/EDSSC.2007.4450266

A 12 bit direct level-signal transition based pipelined analog-to-digital converter. / Hsu, T. Y.; Lin, Zhi-Ming.

IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 881-884 4450266 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

AB - This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

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Hsu TY, Lin Z-M. A 12 bit direct level-signal transition based pipelined analog-to-digital converter. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 881-884. 4450266. (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450266