This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source. The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35 μm 2P4M technology. The power consumption was approximately 7.9 mW at the sample rate of 200 MHz, and the supply voltage was 3.3 V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3 dB under a 1 MHz sine waveform. This work presented a good performance compared with other researches in DNL, INL and power consumption.
|Number of pages||4|
|Journal||AEU - International Journal of Electronics and Communications|
|Publication status||Published - 2015 Jan|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering